Misfet (Metal -insulator-semiconductor field-effect transistor) logical circuit having depletion type load transistor

ABSTRACT

In a logic circuit having a load MISFET of the depletion type, a MISFET logic circuit employs a logic block of a predetermined logic expression, and a MISFET of the enhancement type. The depletion type MISFET, the logic block and the enhancement type MISFET are connected in series. The enhancement type MISFET is driven by clock pluses so that, only when it is conductive, current flows through the series circuit. Thus, the amount of power consumption is lowered.

United States Patent Hatsukano Nov. 4, 1975 MISFET (METAL 3,772,53611/1973 Grannis 307/205 x .INSULATOR SEMICONDUCTOR 3,783,306 l/ 1974Hoffmann 307/205 X FIELD-EFFECT TRANSISTOR) LOGICAL CIRCUIT HAVINGDEPLETION TYPE LOAD OTHER PUBLICATIONS Fette, Dynamic Mos A LogicalChoice; EDN/EEE TRANSSTOR (pub.); 11/15/1971, CH6-CH14. [75] Inventor:Yoshikazu Hatsukano, Kodaira, Lohman, Applications of MOS FETs inMicroelec- Japan tronics; SCP and Solid State Technology (pub.), 73Assignee: Hitachi, Ltd., Japan 3/1966; i

Rutherford, Time D1v1s1on Multiplex Modulator for [22] Fund: July 23,1973 Multiphase Dynamic FET Logic; IBM Tech. Discl. [21] Appl. No.:381,485 Bull.; Vol. 14, No. 7, pp. 1982; 12/1971.

Yen, Computer-Aided Test Generation for Four 30 F A H D Phase MOS LS1Circuits, IEEE Transactions on 1 PP Computers, VOl. C18, N0. 10;10/1969; 890-893.

Aug. 25, 1972 Japan 47-84565 Prima ExaminerMichael J. L nch [52] US.Cl.2 307/205; 307/215', 307/221 C AssisgmExaminer L Anagzlos [51]Attorney, Agent, or F irm-Craig & Antonelli [58] Field of Search307/205, 214, 215, 218,

307/304, 279 1571 ABSTRACT In a logic circuit having a load MISFET ofthe deple- [56] References Cited tion type, a MISFET logic circuitemploys a logic UNITED STATES PATENTS llglgi k off ztahpredelterminedlogic explrplssipin, land a MIS- 3,299,291 l/l967 Warner, Jr. et a1307/214X 0 6 en i type e ep type 3,497,715 2/1970 Yen 307/205 MISFET thelog: and enhancement type 3,517,210 6/1970 Rubinstein 307/205 MISFET areqonngcted Senes- The enhancement 3,601,627 8/1971 Booher 307/205 ypMISFET 1S drlven y Clock pluses so that, y 3,638,036 1/1972 Zimbelmann307/205 when it is conductive, current flows through the series3,683,201 8/1972 Haraszti 307/205 circuit, Thus, the amount of powerconsumption is 3,700,981 10/1972 Masuhara et a 307/205 X 1 3,731,1145/1973 Gehweiler 307/205 3 Claims, 5 Drawing Figures Voo 012 Qla Q14 1 QGd? Qd i \buf :VE V6 V0 H I 0 I I i l I I Qd 1 Qda 1, I

US. Patent Nov. 4, 1975 Sheet 2 of2 3,917,958

FIG. 4

FIG. 5

Vout Vm -I Qd MISFET (METAL- INSULATOR-SEMICONDUCTOR FIELD-EFFECTTRANSISTOR) LOGICAL CIRCUIT HAVING DEPLETION TYPE LOAD TRANSISTORBACKGROUND OF THE INVENTION 1. Field of the Invention The presentinvention relates to a logic circuit composed of insulated gatefield-effect transistors (hereinbelow termed MlSFETs). Moreparticularly, it relates to a MISFET logic circuit having a depletiontype load transistor.

2. Description of the Prior Art As the general logic circuit employingMISFETs, the so-called EE(enhancementenhancement) system is known inwhich both MISFETs for a load and for drive are of the enhancement type.As means to reduce the power consumption of the above system, there isthe clock drive system in which the load transistor is driven by clockpulses.

On the other hand, with the so-called ED (enhancement-depletion) systememploying a depletion type MISFET as a load transistor, it is difficultto adopt the clock drive system similar to that of the BE system.Nevertheless, excellent properties such as low power consumption, highspeed and high degree of integration are available due to thepossibility of a low supply voltage and the constant currentcharacteristic of the depletion type MISFET.

FIG. shows the fundamental circuit of a logic circuit according to theED system.

To be noted in regard to the fundamental circuit in the figure is thefact that, whenever drive transistor Q is conductive, current flowsthrough a series circuit consisting of the drive transistor 0,, and loadtransistor Q SUMMARY OF THE INVENTION It is, accordingly, an object ofthe present invention to reduce the average quantity of current whichflows through the series circuit, to thereby further lower the powerconsumption of a logic circuit according to the ED system.

Another object of the present invention is to provide a MISFET logiccircuit having a depletion type load transistor, which circuit can bebrought into a low power consumption without significantly increasingthe number of transistors.

The present invention itself and the other objects of the presentinvention will become apparent from the following detailed descriptionwhen taken with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 to 3 are connection diagramsof MISFET logic circuits employing depletion type load transistorsarranged in accordance with the present invention;

FIG. 4 is a time chart for explaining the operation of the shiftregister in FIG. 3; and

FIG. 5 is a prior-art MISFET logic circuit employing a depletion typeload transistor, which circuit has already been referred to.

PREFERRED EMBODIMENTS OF THE INVENTION FIG. 1 shows a MISFET logiccircuit according to the present invention.

In the figure, Q11 designates a MISFET of the depletion type by which,even when no bias voltage is applied between the gate and the source,current flows between the source and the drain. The depletion typeMISFET O is used as a load transistor. On the other hand, Q Q indicateMISFETs of the enhancement type by which, when a prescribed bias voltageis applied between the gate and the source, current will begin to flowbetween the source and the drain. The enhancement type MISFETs are usedas drive transistors.

In order to provide a good constant current charac' teristic, the gateelectrode of the MISFET Q" is connected to the source electrode thereof,namely, the output terminal of the logic circuit.

The MISFETs Q, Q constitute a logic block LB which satisfies the logicexpression V (V V,,) V (when the conductivity type of the channel ofeach MISFET is P-type and when positive logic is adopted).

A MISFET Q is further provided by the present invention. It has clockpulses 4) applied to the gate electrode and is, thus, clock-driven. Thepulse width of the clock pulse 4) is made smaller than the pulse widthof each of the input signals V V The MISFETs Q11 and Q. and the logicblock LB are connected in series. The output signal V is derived fromthe connection between the logic block LB and the load MISFET QAccording to the present invention, however, it is also possible toconnect the transistor Q between the load MISFET Q and the logic blockLB, and to derive the output signal from the drain electrode of thetransistor Qai.

With the MISFET logic circuit thus constructed, only when the MISFET Q,is rendered conductive by the clock pulse (b, will current flow throughthe closed series circuit consisting of the MISFETs Q11 and Q4 and thelogic block LB. It is, therefore, possible to reduce the powerconsumption. The value of the output signal V is determined by thevalues of the input signals V V during the conduction period of MISFET QThat is, the relation V (V V V holds during the conduction period.

With the MISFET logic circuit according to the present invention, thenumber of transistors which are serially connected between the outputterminal and a ground terminal is increased by one in comparison withthe number of the same in a circuit of the EB system. However, the areaoccupied by the elements does not become larger, but it becomes smallerunder some conditions.

The reason is that, with the BE system, the number of transistors to beconnected in series from the output terminal is limited to at most two,whereas with the ED system, about four transistors can be connected inseries from the output terminal under the condition of obtaining thesame output level at the same operating speed.

A quantitative explanation of the reason will be omitted for brevity. Inshort, it is with the ED system that the connection of the currentlimiting MISFET in series with the logic block LB can be readilyaccomplished.

FIG. 2 shows another embodiment according to the present invention,which is an AND OR circuit often required in a digital control circuit,etc.

In the figure, Q Q indicate enhancement type MISFETs. With a respectivepair of the transistors forming each set, logic blocks LB LE areconstructed. Depletion type load MISFETs Q12 Q14 are connected to therespective logic blocks. Each of the 3 logic blocks LB, L8 is soarranged as to have the function of a two-input NAND circuit. Outputsignals derived from the logic blocks LB, and LE are utilized as inputsignals of the logic block L8 It will be understood that output signal Vis, accordingly, represented by the logic expression:

v,,,, v .'v",; v. v.,- v,, v, V,- v

The feature of the AND OR circuit lies in that a single MISFET Q isconnected commonly in series to the respective logic blocks, whereby thecurrent flowing through the three logic blocks is limited by the singletransistor Q Even with such an arrangement, the actual logic issimilarly determined during the period of the width of the clock pulseapplied to the transistor dll' In this manner, according to thisembodiment, a single MISFET may be provided for an aggregate of logicblocks. The embodiment, therefore attains the object of reducing thepower consumption, and is advantageous 'in being capable of increasingthe degree of integration.

The single MISFET must usually absorb the total amount of currentflowing through the logic blocks belonging to the aggregate to which theMISFET is connected. In consequence, it must be a MISFET larger (lowerin resistance) than the transistors constituting the logic blocks. Ofcourse, in addition to the form of the single MISFET, the currentlimiting MISFET may take the form of a plurality of MISFETs connected inparallel. Since the logic is not dynamic, using a fourphase clock, theembodiment also has the feature that the current limiting MISFET may bearranged at a place convenient for layout.

FIG. 3 shows still another embodiment of the present invention, which isa'two-phase dynamic shift register of two bits.

In the figure, enhancement type MISFETs Qmz Q are connected to depletiontype load MISFETs Q, Q respectively. An enhancement type MISFET forcurrent limitation Q is connected commonly in series to the MISFETs Qd12and Q and its gate electrode is applied with clock pulses (b as shown inFIG. 4, A MIS- FET Q is connected commonly in series to the MIS- FETsQdli; and 0, and its gate electrode is applied with clock pulses 4);(FIG. 4) which differ in phase from the clock pulses 4) The MISFETs Q 0,and Q constitute an inverter circuit. Similarly, the other MISFETs(including 0, constitute three inverter circuits. The respectiveinverter circuits are connected in cascade through enhancement typeMISFETs for transfer 0,, Q From the inverter circuit at the final stage,an output signal is derived through a MISFET Q The gate electrodes ofthe MISFETs Q and 0, are applied with the clock pulses (in, while thegate electrodes of the MISFETs 0, and Q are applied with the clockpulses qb The gate electrode of the MISFET 0, is applied with an inputsignal V (FIG. 4) which is synchronized with the clock pulses (1) Theoperation of the shift register thus constructed will now be describedwith reference to the time chart in FIG. 4. In the figure, the upperlevel indicates a logical 1 (ground potential), and the lower level alogical 0 (a negative potential).

When the clock pulse becomes 0 to render the MISFET Q conductive, anoutput signal of the first inverter circuit or the source potential V ofthe MIS- FET Q becomes the inverted signal V,-,, of the input signalV,-,,. Since the transfer MISFET 0,, is also conductive at this time,the output signal V is fed through the MISFET Q to the MISFET Q0113, andis stored by the gate capacitance of the MISFET Q Similarly, when theclock pulse (15 becomes 0 to render the MIS- FETs Q and Q conductive,the inverted signal of the signal stored in the MISFET Q is written intothe gate capacitance of the MISFET Qa Accordingly, the gate potential Vof the MISFET Qdlii becomes equal to a signal with the inverted signalof the input signal V delayed by the phase difference between the clockpulses d), and (1) as the gate potential V is synchronized with theclock pulse 11 and the input signal V is synchronized with the clockpulse (1) Since the periods of the clock pulses (b, and 4J are equal,the gate potential of the MISFET Q ultimately becomes equal to a signalwith the input signal V delayed by one period (one bit) of the clockpulses d), or (1) This is also apparent from the time chart in FIG. 4. i

As illustrated in FIG. 4, the output potential V of the first inverteris forced to the value 0 irrespective of the input signal when the clockpulse d) is held at 1. Only when the clock pulse d falls to O, is theoutput potential V transferred through the MISFET Q to the MIS- FET Qd13and written thereinto. The gate potential V therefore sustains only thecorrect value of the output potential V until the clock pulse (11subsequently changes to 1. For a similar reason, the period during whichthe output potential V exhibits the correct value becomes equal to thepulse width of the clock pulse 5 and is shorter than such period of theinput signal V However, this causes no problem since the period duringwhich the gate potential V exhibits the correct value becomes equal tothe period of the clock pulses 4:-

In this manner, the period during which the output signal derived fromeach logic block indicates the correct value is made short with respectto the pulse width of the clock pulse. When it must be corrected, thelogic circuit in FIG. 1, for example, may be operated such that thesignal is fed from the logic block LB to the next stage of the circuitthrough the transfer MISFET which is triggered by the clock pulse Theshift register described above has the following advantages, which willbe easily understood from the explanation of the embodiments in FIGS. 1and 2:

l. The power consumption is lowered; and

2. The number of transistors for lowering the power consumption can bemade smaller than the number of logic blocks.

What I claim is:

1. A MISFET logic circuit comprising:

a first terminal to which a source of D.C. potential is supplied;

a second terminal serving as a common terminal;

a third terminal to which ground potential is applied;

a plurality of depletion type MISFETs each having a drain electrodeconnected to said first terminal, and a source electrode and a gateelectrode connected together;

a plurality of logic blocks, each having a reference terminal, an outputterminal, and at least one input terminal, the output terminals beingconnected to the respective source electrodes of said depletion typeMISFETs and the reference terminals being connected to said secondterminal, each of said logic blocks comprising at least one firstenhancement type MISFET having a drain electrode connected to the outputterminal thereof, a gate electrode connected to a respective inputterminal, and a source electrode coupled to the reference terminalthereof;

a second enhancement type MISFET having a resistance lower than said atleast one first enhancement MISFET and having a drain electrodeconnected to said second terminal, a source electrode connected to saidthird terminal, and a gate electrode;

means for supplying a clock pulse signal to the gate electrode of saidsecond enhancement type MIS- FET; and

means for supplying input signals to said input terminals, therebycausing the logic functions to be effected by said logic blocks onlyduring the period of the width of the clock pulse.

2. A MISFET logic circuit comprising:

first and second depletion type MlSFETs, each having a drain electrode,a source electrode, and a gate electrode connected to the sourceelectrode;

a first terminal serving as a common terminal;

a second terminal to which ground potential is applied;

a first logic block having a reference terminal, an output terminal andat least one input terminal, said output terminal being connected to thesource electrode of said first depletion type MISFET and said referenceterminal being connected to said common terminal, said first logic blockincluding at least one first enhancement type MISFET having a drainelectrode electrically connected to said output terminal, a sourceelectrode coupled to said reference terminal and a gate electrodeconnected to a respective input terminal;

a second logic block having a reference terminal, a

output terminal and at least one input terminal, the output terminalbeing connected to the source electrode of said second depletion typeMISFET and the reference terminal being connected to said commonterminal, said second logic block including at least one secondenhancement type MISFET having a drain electrode connected to the outputterminal, a gate electrode connected to a respective input terminal, anda source electrode coupled to the reference terminal;

a third enhancement type MISFET having a resistance lower than the firstand second enhancement type MISFETs and having a drain electrode con- 6nected to said common terminal, thereby commonly connecting thereference terminals of said first and second logic blocks, a sourceelectrode connected to said second terminal, and a gate electrode;

means for supplying an electrical potential to the drain electrodes ofsaid first and second depletion type MlSFETs;

means for supplying a clock pulse signal to the gate electrode of saidthird enhancement type MISFET;

means for supplying an input signal to the input terminal to which thegate electrode of one of said at least one first enhancement type MISFETof said first logic block is connected; and

wherein the output terminal of said first logic block is connected tothe gate electrode of one of said at least one second enhancement typeMISFET of said second logic block.

3. A MISFET logic circuit comprising:

a depletion type MISFET having a drain electrode, a source electrode anda gate electrode connected to said source electrode;

a common terminal;

a ground terminal;

a logic block connected between the source electrode of said depletiontype MISFET and said common terminal, said logic block being constructedby a plurality of signal paths each having at least one firstenhancement type MISFET having a drain electrode electrically connectedto the source electrode of said depletion type MISFET, a sourceelectrode and a gate electrode, all of the signal paths being terminatedat said common terminal;

a second enhancement type MISFET having a resistance lower than said atleast one first enhancement type MISFET when conducting and having adrain electrode connected to said common terminal, a source electrodeconnected to said ground terminal, and a gate electrode;

means for supplying an electrical potential to the drain electrode ofsaid depletion type MISFET;

means for supplying a clock pulse signal to the gate electrode of saidsecond MISFET; and

means for supplying input signals to the gate electrodes of said firstenhancement type MISFETs in said logic block.

1. A MISFET logic circuit comprising: a first terminal to which a sourceof D.C. potential is supplied; a second terminal serving as a commonterminal; a third terminal to which ground potential is applied; aplurality of depletion type MISFETs each havinG a drain electrodeconnected to said first terminal, and a source electrode and a gateelectrode connected together; a plurality of logic blocks, each having areference terminal, an output terminal, and at least one input terminal,the output terminals being connected to the respective source electrodesof said depletion type MISFETs and the reference terminals beingconnected to said second terminal, each of said logic blocks comprisingat least one first enhancement type MISFET having a drain electrodeconnected to the output terminal thereof, a gate electrode connected toa respective input terminal, and a source electrode coupled to thereference terminal thereof; a second enhancement type MISFET having aresistance lower than said at least one first enhancement MISFET andhaving a drain electrode connected to said second terminal, a sourceelectrode connected to said third terminal, and a gate electrode; meansfor supplying a clock pulse signal to the gate electrode of said secondenhancement type MISFET; and means for supplying input signals to saidinput terminals, thereby causing the logic functions to be effected bysaid logic blocks only during the period of the width of the clockpulse.
 2. A MISFET logic circuit comprising: first and second depletiontype MISFETs, each having a drain electrode, a source electrode, and agate electrode connected to the source electrode; a first terminalserving as a common terminal; a second terminal to which groundpotential is applied; a first logic block having a reference terminal,an output terminal and at least one input terminal, said output terminalbeing connected to the source electrode of said first depletion typeMISFET and said reference terminal being connected to said commonterminal, said first logic block including at least one firstenhancement type MISFET having a drain electrode electrically connectedto said output terminal, a source electrode coupled to said referenceterminal and a gate electrode connected to a respective input terminal;a second logic block having a reference terminal, an output terminal andat least one input terminal, the output terminal being connected to thesource electrode of said second depletion type MISFET and the referenceterminal being connected to said common terminal, said second logicblock including at least one second enhancement type MISFET having adrain electrode connected to the output terminal, a gate electrodeconnected to a respective input terminal, and a source electrode coupledto the reference terminal; a third enhancement type MISFET having aresistance lower than the first and second enhancement type MISFETs andhaving a drain electrode connected to said common terminal, therebycommonly connecting the reference terminals of said first and secondlogic blocks, a source electrode connected to said second terminal, anda gate electrode; means for supplying an electrical potential to thedrain electrodes of said first and second depletion type MISFETs; meansfor supplying a clock pulse signal to the gate electrode of said thirdenhancement type MISFET; means for supplying an input signal to theinput terminal to which the gate electrode of one of said at least onefirst enhancement type MISFET of said first logic block is connected;and wherein the output terminal of said first logic block is connectedto the gate electrode of one of said at least one second enhancementtype MISFET of said second logic block.
 3. A MISFET logic circuitcomprising: a depletion type MISFET having a drain electrode, a sourceelectrode and a gate electrode connected to said source electrode; acommon terminal; a ground terminal; a logic block connected between thesource electrode of said depletion type MISFET and said common terminal,said logic block being constructed by a plurality of signal paths eachhaving at least one first enhancement type MISFET having a drainelectrode electrically connected to the source electrode of saiddepletion type MISFET, a source electrode and a gate electrode, all ofthe signal paths being terminated at said common terminal; a secondenhancement type MISFET having a resistance lower than said at least onefirst enhancement type MISFET when conducting and having a drainelectrode connected to said common terminal, a source electrodeconnected to said ground terminal, and a gate electrode; means forsupplying an electrical potential to the drain electrode of saiddepletion type MISFET; means for supplying a clock pulse signal to thegate electrode of said second MISFET; and means for supplying inputsignals to the gate electrodes of said first enhancement type MISFETs insaid logic block.